MOS Capacitors
Pinhole Free Glassivation SLC Capacitor Wafer Level S Parameter Consistency MOS Cap Chip For Fine Capacitance Step
Custom MOS Capacitor Pinhole Free Glassivation Passivation Wafer Level S Parameter Consistency Fine Capacitance Step HACC-CUSTOM-GS: Pinhole-Free Glassivation MOS Capacitor with Wafer-Level S-Parameter Consistency & Fine Capacitance Step Advanced Pinhole-Free Glassivation & Passivation MOS capacitor reliability in harsh environments — particularly high-humidity, high-temperature operating conditions — is dominated by the quality of the passivation and glassivation layers. A
Ultra Low ESR Fine Capacitance Step Wire Bond Capacitor Precision Tuning High Capacitance Capacitor For Multi Gigabit
Custom MOS Capacitor Ultra Low ESR Multi Gigabit Fine Capacitance Step Precision Tuning Wire Bond Optimized Surface HACC-CUSTOM-ES: Ultra-Low ESR MOS Capacitor for Multi-Gigabit SERDES with Fine Capacitance Step & Wire-Bond Optimized Surface Engineered Ultra-Low ESR for Multi-Gigabit Links Multi-gigabit SERDES (Serializer/Deserializer) DC blocking capacitors face stringent equivalent series resistance (ESR) requirements. At 10 Gbps and beyond, even 0.1 Ohm of ESR contributes
Custom RF Chip Capacitor Radiation Hardened Space Capacitor Flat Q Response Digital Wafer Map
Custom MOS Capacitor Rad Hard Radiation Hardened Space Flat Q Response Digital Wafer Map Automated Sorting HACC101S10V500: Radiation-Hardened MOS Capacitor for Space with Digital Wafer Map & Flat-Q Response Radiation-Hardened Formulations for Space The HACC101S10V500 is specifically designed and qualified for space environments where total ionizing dose (TID) radiation degrades standard MOS structures. The radiation-hardened gate oxide — using nitrided SiO₂ or hardened Al₂O₃
Flat Q Response Low ESR Capacitor Ultra Low Dielectric Absorption Eutectic Backside Ceramic Chip Capacitor
Custom MOS Capacitor Eutectic Backside Metallization Flat Q Response Ultra Low Dielectric Absorption HACC-CUSTOM-BM: Eutectic-Optimized MOS Capacitor with Flat-Q Response & Ultra-Low Dielectric Absorption Customized Backside Metallization for Eutectic Soldering The HACC-CUSTOM-BM offers customer-selectable backside metallization stacks optimized for eutectic die attach processes. Three gold-based eutectic alloy systems are available, selected based on your assembly thermal
Extreme Voltage Dielectric Single Layer Ceramic Capacitor Wafer Level High Capacity Capacitor With Gel Pak Delivery
Custom MOS Capacitor Dielectric Thickness Extreme Voltage Wafer Level Gel Pak Delivery Doping Resistivity Control HACC-CUSTOM-DV: Extreme-Voltage MOS Capacitor with Flexible Wafer-Level & Gel-Pak Delivery Customized Dielectric Thickness for Extreme Voltages The HACC-CUSTOM-DV extends the single-layer MOS capacitor voltage range through engineered dielectric thickness. The standard thermally grown SiO₂ dielectric (50–5000Å) supports rated voltages up to 500V. For higher
Substrate Doping Resistivity Control Custom Capacitors Irregular Die Geometry MOS Capacitor Binary Array Chip
Custom MOS Capacitor Substrate Doping Resistivity Control Array Layouts Irregular Die Geometry Binary Capacitor Arrays HACC100S10V101: Substrate-Engineered MOS Capacitor with Binary Arrays & Irregular Die Geometry Tailored Substrate Doping & Resistivity Control The HACC100S10V101 offers customization of the silicon substrate electrical properties as a design parameter — not a fixed foundry default. N+ or P+ doping profiles are tailored to achieve target resistivity from 0.001
Rapid Prototyping MOS Capacitors Flexible Customization 10 pF Capacitor Eco Friendly Supply Chain Compliant Chip
The HACC100S10V101 is a 10pF 100V Single-Sided Bordered Single Layer Ceramic Capacitor (SLC) designed for customers requiring flexible customization, rapid prototyping turnaround, and full regulatory compliance documentation. With configurable capacitance tolerance (±10% standard, ±5% available), dielectric options (Class I COG/NPO or Class II X7R), and supported by rapid wafer-level prototyping with 3-4 week lead times, this capacitor accelerates RF module development from concept to qualification. Full RoHS, REACH, and halogen-free compliance documentation is provided per production lot. The TiW-Au (≥2.5µm) top and TiW-Pt-Au (≥2.5µm) bottom electrodes ensure reliable wire bonding and universal die-attach compatibility with epoxy, AuSn eutectic, and sintered-Ag processes.
Guard Ring Passivation 10 pF Capacitor High Power Low PIM Low ESR Capacitor Advanced Backside Metal Chip
The HACC100S10V101 is a 10pF 100V Single-Sided Bordered Single Layer Ceramic Capacitor (SLC) featuring TiW-Au (≥2.5µm Au) top and TiW-Pt-Au (≥2.5µm Au) bottom metallization for diverse mounting compatibility. The guard-ring and edge passivation design suppresses surface leakage currents, while the single-layer coaxial architecture delivers high power handling with ultra-low PIM (Passive Intermodulation). ESR below 0.1Ω at 1GHz ensures minimal insertion loss in high-frequency signal paths. Operating from -55°C to +125°C with 250% rated DWV margin (100V→250V), this device is engineered for 5G mmWave, GaN power amplifier bypass, and satellite communication applications requiring reliable performance under demanding conditions.
High Breakdown Voltage MOS Capacitors Ultra Miniature Low Leakage 50V Wire Bondable Capacitor SLC Chip
The HACC101S10V500 is a 100pF 50V ultra-miniature single-layer MOS capacitor featuring high breakdown voltage exceeding 125V (>2.5x rated) and ultra-low leakage current below 10nA at rated voltage. Fabricated on high-resistivity silicon substrate with thermally-grown SiO2 dielectric and 2.5μm minimum gold metallization, the wire-bondable top electrode supports thermosonic Au ball bonding and Al wedge bonding with >6gf pull strength. Packaged in an ultra-compact 0.50×0.50×0.15mm chip, this device enables high-density integration in hybrid microcircuits, phased-array T/R modules, and space-constrained RF front-end assemblies. Backside TiW-Pt-Au metallization with Pt barrier ensures compatibility with silver epoxy and AuSn eutectic die attach.
Ultra Low Loss MOS Capacitors Excellent TCC VCC Stability 100pF 50V High Q Capacitor At RF
The HACC101S10V500 is a 100pF 50V single-layer MOS capacitor fabricated on high-resistivity silicon substrate with thermally-grown SiO2 dielectric and 2.5μm gold metallization. Delivering Q factor exceeding 2000 at 1MHz and maintaining Q above 200 at 1GHz, this device achieves exceptionally low ESR below 0.1Ω for minimal insertion loss in RF signal paths. With TCC below 30ppm/°C and VCC below 50ppm/V, capacitance remains stable across the full -55°C to +125°C operating range. Designed for broadband DC blocking, RF coupling, and impedance matching in microwave circuits from 1MHz to 20GHz.
Ultra Low Total Harmonic Distortion MOS Capacitors Zero Dielectric Dispersion 100 pF 50V Single Layer Chip For Analog
HACC101S50V601 100pF 50V MOS Capacitor Ultra Low Total Harmonic Distortion Zero Dielectric Dispersion Paraelectric SiO2 Single Layer Chip The HACC101S50V601 is a 100pF ±10% single-layer MOS capacitor rated at 50V DC, fabricated on float-zone silicon (>1000 Ω·cm) with an amorphous paraelectric thermal SiO2 dielectric and TiW-Au / TiW-Pt-Au metallization. Standard chip dimensions are 0.50mm × 0.50mm × 0.15mm (±25µm). Because thermal SiO2 is paraelectric (no ferroelectric
Advanced Dielectric Passivation MOS Capacitors Step Edge Geometry 1000 pF 100V Single Layer Chip For Arc Over Prevention
HACC102S100V301 1000pF 100V MOS Capacitor Advanced Dielectric Passivation Step Edge Geometry Moisture Resistant Single Layer Chip The HACC102S100V301 is a 1000pF ±10% single-layer MOS capacitor rated at 100V DC, fabricated on float-zone silicon (>1000 Ω·cm) with an amorphous thermal SiO2 dielectric and TiW-Au / TiW-Pt-Au metallization. Standard chip dimensions are 0.75mm × 0.75mm × 0.20mm (±25µm), with custom capacitance, voltage rating, die geometry (aspect ratio up to 4:1),
Extreme High Temp 200C 100pF 30V MOS Capacitor Superior ESD Tolerance Single Layer RF Chip for Harsh Environments
HACC101S30V200 Extreme High-Temperature MOS Capacitor: 100pF 30V with 200°C Continuous Operation and Superior ESD Tolerance The HACC101S30V200 is a 100pF ±10% single-layer MOS capacitor rated at 30V DC, engineered for continuous operation at temperatures up to 200°C—substantially exceeding the industry-standard 125°C limit for conventional MOS capacitors. Fabricated on float-zone silicon (>1000Ω·cm) with 300nm thermally-grown SiO2 dielectric, this device incorporates a
Low Dissipation Factor 50pF 50V MOS Capacitor Custom Metal Metallization SLC Chip for RF Power Packaging
HACC500S50V500 Custom Low Dissipation Factor MOS Capacitor 50pF 50V Minimal Tan δ Under RF Power — Fully Customizable Metal Layout & Geometry The HACC500S50V500 is a fully customizable 50 pF 50 V single-layer MOS capacitor featuring industry-leading low dissipation factor (tan δ < 0.001 at 1 GHz) verified under full RF power excitation up to +40 dBm (10 W) continuous wave . With a fully configurable metal layout—including selective gold thickness, patterned multi-pad
Zero Dielectric Memory 1000pF 80V MOS Capacitor Ultra-Linear CV Characteristics Paraelectric SiO2 Single Layer RF Chip
HACC102S80V500 Zero Dielectric Memory MOS Capacitor: 1000pF 80V with Ultra-Linear C-V Characteristics and Paraelectric SiO2 Dielectric The HACC102S80V500 is a 1000pF ±10% single-layer MOS capacitor rated at 80V DC, fabricated on float-zone silicon (>1000Ω·cm) with 300nm thermally-grown paraelectric SiO2 dielectric. Chip dimensions are 0.75mm × 0.75mm × 0.15mm with TiW-Au top metallization (2.5µm minimum Au) and TiW-Pt-Au backside (1.0µm minimum Au, Pt barrier). This device is
Ultra Small 0.40mm Bare Die Radiation Hardened 47pF 50V MOS Capacitor Zero Piezoelectric Noise Single Layer Chip
HACC470S50V160 Ultra-Small Radiation Hardened MOS Capacitor 47pF 50V Zero Piezoelectric Noise Bare Die Chip The HACC470S50V160 is a 47pF ±10% single-layer MOS capacitor rated at 50V DC, fabricated on high-resistivity float-zone silicon (>1000 Ω·cm) with 300nm thermally-grown amorphous SiO₂ dielectric. With an ultra-miniature footprint of just 0.40 * 0.40 * 0.15mm (16mil * 16mil * 6mil) — a 36% area reduction versus standard 0.50mm chips — this device enables capacitor
Custom High Q Ultra-Low ESL 470 pF MOS Capacitor Wire Bondable Single Layer Chip for RF Microwave Circuits
HACC471S20V500 Custom High Q Ultra-Low ESL MOS Capacitor 470pF 20V Wire-Bondable Single Layer Chip The HACC471S20V500 is a high-performance, fully customizable Single Layer MOS capacitor fabricated on high-resistivity float-zone silicon substrate (>1000 Ohm·cm) with 300nm thermally-grown SiO2 dielectric. Rated at 470pF ±10% with 20V DC continuous operating voltage, this device combines High Q factor , Ultra-Low ESL/ESR , Exceptional Capacitance Stability , and Wire-Bondable
High-K Dielectric 330pF 25V MOS Capacitor Ultra-Low Phase Noise Wire Bondable Single Layer Chip for VCO PLL Circuits
HACC331S25V500 Custom High-K Dielectric MOS Capacitor 330pF 25V Ultra-Low Phase Noise for VCO & PLL Circuits — Fully Customizable The HACC331S25V500 is a fully customizable 330 pF 25 V single-layer MOS capacitor featuring an engineered high-K composite dielectric stack (SiO&sub2;/Al&sub2;O&sub3;/HfO&sub2;) that achieves 1,320 pF/mm² areal capacitance density —over 3× the density of conventional SiO&sub2;-only MOS capacitors—while delivering ultra-low phase noise below -16
Miniaturized High-Density 220pF 30V MOS Capacitor Exceptional High-Frequency Stability Wafer-Level Custom SLC Chip
HACC221S30V120 Miniaturized High-Density MOS Capacitor: 220pF 30V with Exceptional High-Frequency Stability and Wafer-Level Customization The HACC221S30V120 is a 220pF ±10% single-layer MOS capacitor rated at 30V DC, fabricated on float-zone silicon (>1000Ω·cm) with 300nm thermally-grown SiO2 dielectric. With an ultra-miniature footprint of just 0.35 x 0.35 x 0.15mm — a 51% area reduction versus standard 0.50mm chips — this device achieves an industry-leading capacitance
Custom High Breakdown Voltage Low Leakage 1000 pF MOS Capacitor Ultra Stable TCC Wire Bondable Chip for RF Bypass
HACC102S80V750 Custom High Breakdown Voltage MOS Capacitor 1000pF 80V Ultra-Stable TCC Low Leakage Wire-Bondable Chip The HACC102S80V750 is a high-reliability, fully customizable Single Layer MOS capacitor engineered for applications demanding High Breakdown Voltage , Ultra-Low Leakage Current , and Exceptional Capacitance Stability over Temperature and Voltage . Fabricated on high-resistivity float-zone silicon substrate (>1000 Ohm·cm) with 300nm thermally-grown SiO2