LV810FILFT Clock Drivers & Distribution Buffer/Clock Driver Integrated Circuits ICs

LV810FILFT Clock Drivers & Distribution BUFFER/CLOCK DRIVER Integrated Circuits ICs

Description

The ICSLV810 is a low skew 1.5 V to2.5 V, 1:10 fanout
buffer. This device is specifically designed for data
communications clock management. The large fanout from
a single input line reduces loading on the input clock. The
TTL level outputs reduce noise levels on the part. Typical
applications are clock and signal distribution.

Features
●Packaged in 20-pin QSOP/SSOP
●Split 1:10 fanout Buffer
●Maximum skew between outputs of different packages
  0.75 ns
●Max propagation delay of 3.8 ns
●Operating voltage of 1.5 V to 2.5 V on Bank A
●Operating voltage of 1.5 V to 2.5 V on Banks B and C
●Advanced, low power, CMOS process
●Industrial temperature range -40° C to +85° C
●3.3 V tolerant input when VDDA=2.5 V
●Pb (lead) free packaging

Description

The ICSLV810 is a low skew 1.5 V to2.5 V, 1:10 fanout
buffer. This device is specifically designed for data
communications clock management. The large fanout from
a single input line reduces loading on the input clock. The
TTL level outputs reduce noise levels on the part. Typical
applications are clock and signal distribution.

Features
●Packaged in 20-pin QSOP/SSOP
●Split 1:10 fanout Buffer
●Maximum skew between outputs of different packages
0.75 ns
●Max propagation delay of 3.8 ns
●Operating voltage of 1.5 V to 2.5 V on Bank A
●Operating voltage of 1.5 V to 2.5 V on Banks B and C
●Advanced, low power, CMOS process
●Industrial temperature range -40° C to +85° C
●3.3 V tolerant input when VDDA=2.5 V
●Pb (lead) free packaging

External Components
The ICSLV810 requires a minimum number of external
components for proper operation.
Decoupling Capacitors
Decoupling capacitors of 0.01μF must be connected
between VDD and GND, as close to these pins as possible.
For optimum device performance, the decoupling capacitors
should be mounted on the component side of the PCB.
Avoid the use of vias in the decoupling circuit.
Series Termination Resistor
When the PCB trace between the clock outputs and the
loads are over 1 inch, series termination should be used. To
series terminate a 502 trace (a commonly used trace
impedance) place a 33Q2resistor in series with the clock line,

as close to the clock output pin as possible. The nominal
impedance of the clock output is 202
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1) The 0.01μF decoupling capacitors should be mounted on
the component side of the board as close to the VDD pins
as possible. No vias should be used between the
decoupling capacitors and VDD pins. The PCB trace to VDD
pin should be kept as short as possible, as should the PCB
trace to the ground via.
2) To minimize EMI the 332 series termination resistor, if
needed, should be placed close to the clock output.