10M50DDF484I7G Programmable Logic IC Field Programmable Gate Array 484-BGA Package

10M50DDF484I7G Programmable Logic IC Field Programmable Gate Array 484-BGA Package Product Description Of 10M50DDF484I7G 10M50DDF484I7G is third generation Hard Processor System. Leveraging the performance of 14 nm tri-gate technology, the HPS provides more than double the performance of previous generation devices with an integrated quad-core 64-bit Arm Cortex-A53. The HPS also enables system-wide hardware virtualization capabilities by adding a system memory management unit

Operating Temperature -40°C ~ 100°C (TJ)
Place of Origin CN
Part Number 10M50DDF484I7G
Packaging Details 484-BGA
Number of LABs/CLBs 3125
Total RAM Bits 1677312
Product Description

10M50DDF484I7G Programmable Logic IC Field Programmable Gate Array 484-BGA Package

 

Product Description Of 10M50DDF484I7G

10M50DDF484I7G is third generation Hard Processor System. Leveraging the performance of 14 nm tri-gate technology, the HPS provides more than double the performance of previous generation devices with an integrated quad-core 64-bit Arm Cortex-A53. The HPS also enables system-wide hardware virtualization capabilities by adding a system memory management unit.These architecture improvements ensure that devices meet the requirements of current and future embedded markets, including wireless and wireline communications, datacenter acceleration applications.

 

Specification Of 10M50DDF484I7G

Part Number:

10M50DDF484I7G

LVDS:

1.6 Gbps

Ethernet PCS:

10G

Core Performance:

500 MHz

General-Purpose I/O: 

48

Fabric Clocking:

1 GHz

Logic Density:

952 KLE

M20K:

52 Mbits

DMA:

8-Channel

SPI Controller:

4 SPI

 

Features Of 10M50DDF484I7G

  • 40 bit (32 bit + 8 bit ECC) with select packages supporting 72 bit (64 bit + 8 bit ECC)
  • Support for up to 2666 Mbps DDR4 and 2166 Mbps DDR3 frequencies
  • Error correction code (ECC) support including calculation, error correction, writeback correction, and error counters
  • Software Configurable Priority Scheduling on individual SDRAM bursts
  • Fully programmable timing parameter support for all JEDEC-specified timing parameters
  • Multiport front-end (MPFE) scheduler interface to the hard memory controller, which supports the AXI® Quality of Service (QoS) for interface to the FPGA fabric

 

FAQ
Q. Are your products original?
A: Yes, all products are original, new original import is our purpose.
Q:Which Certificates do you have?
A:We are ISO 9001:2015 Certified Company and member of ERAI.
Q:Can you support small quantity order or sample?Is the sample free?
A:Yes,we support sample order and small order.Sample cost is different according to your order or project.
Q:How to ship my order? Is it safe?
A:We use express to ship,such as DHL,Fedex,UPS,TNT,EMS.We can also use your suggested forwarder.Products will be in good packing and ensure the safety and we are responsible to product damage to your order.
Q:What about the lead time?
A:We can ship stock parts within 5 working days.If without stock,we will confirm lead time for you based on your order quantity.

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