Standard PLC Controller With Ladder Diagram / C Program NPN Transistor Output

ladder diagram/standard C program NPN transistor output ARM CortexTM M3 CPU Description: * CPU: ARM CortexTM M3 CPU. * Digital Input: Transistor input, supporting source drain type. * Digital Output: NPN transistor output. * High-Speed Input: 2-way AB input/4-way separate high-speed counting. Specification: Timer 256 100ms timer x206(0.1~3276.7 seconds),10ms timer x46(0.01~327.67 seconds), 1ms timer x4(0.001~32.767 seconds) Counter 235 High-speed Interrupt X0-X5 rising and